Skip to content

FPGA / CPLD

Part of Embedded processing

mcu.fpga

BOM rule hits · not reviewed — A hit means a BOM line matched this category's rules (ruleset 1.0.1+12960cbec977). It is a lead to read, not a located or reviewed circuit; several lines in one category are not several circuits.

Selection parameter template (suggestion)

What one usually states when choosing a circuit of this kind — not the parameters of any design or module listed here, and never a filter.

ParameterSuggested range or common valuesWhere it comes from
Logic elements (K LE)Decisive1 to 500 K LEThis category's own
Vendor familyDecisiveXilinx Artix-7Xilinx SpartanIntel CycloneMAX 10Lattice iCE40Lattice ECP5Gowin GW1N/GW2AAnlogic EG4/EF2This category's own
User I/OImportant20 to 500This category's own
RAM blocks (Kb)Important64 to 10,000 KbThis category's own
High-speed transceiversFor referenceYes / noThis category's own
ConfigurationFor referenceSPI FlashBuilt-in FlashJTAGThis category's own

In the parent's template, not in this one: Core, Clock speed, Flash, RAM, GPIO count, Peripheral interfaces, Operating voltage, Package

Template version 1.0.1+3e52bcb40ed6 (separate from the rules)

Design files with a hit (194)

Next page